Many integrated circuit devices employ metal-oxide-silicon field-effect transistors (MOSFETs) constructed of gate oxide layers and gate electrodes which are stacked on an integrated circuit substrate and source and drain regions formed in the substrate at both sides of the gate electrodes. The source and drain regions contacts include P/N junctions with the substrate.
Many dynamic random access memories (DRAMs), typically high density memories, include arrays of memory cells each composed of one-MOSFET and one-capacitor. These DRAMs are becoming more highly integrated despite the fact that some physical phenomena that may act as limitations to operational stability of the devices therein.
Exemplary conventional DRAM memory cell arrays are shown in FIGS. 1 and 2. Referring to the plan view of FIG. 1 and the sectional view of FIG. 2 taken along the line I–I′ of FIG. 1, field isolation layers 12 are formed in an integrated circuit substrate 10 to define active regions. Gate patterns 20 are arranged on the substrate 10, across the active regions and the field isolation layers 12. The gate patterns 20 are formed of gate oxide layers 14, gate electrodes 16, and hard mask patterns 18. On both sidewalls of the gate patterns 20, gate spacers 22 are formed. Source and drain regions, 24s and 24d, are disposed within the active regions of the substrate 10, between gate patterns 20, forming P/N junctions with the substrate 10.
As devices become more highly integrated, short channel effects and punch-through phenomena may become obstacles to device performance. The short channel and punch-through effects can arise from expansion of depletion regions associated with the P/N junctions formed by the source and drain regions, relative to channel widths, in devices formed with, for example, sub 1 micron gate patterns.
Several techniques have been proposed to overcome short channel effects and punch-through effects, such as a formation of shallow junctions for the source and drain regions and a use of silicon-on-insulator (SOI) substrates. However, the shallow junctions may increase junction leakage currents (although those structures may help reduce the short channel effect). The SOI substrates may contribute to floating body effects, inefficient properties for heat transmission, and high cost productivity (although SOI may reduce the short channel effects, junction leakage currents, and junction capacitance because P/N junctions do not exist under impurity regions).